With increased operation speed and improved functions of semiconductor integrated circuits, so-called EMI countermeasure for controlling radiated noise to be within a regulated value have especially become difficult. Thus, it sometimes happens that even if EMI countermeasure components, such as an EMI filter or a decoupling capacitor, are mounted on a printed circuit board, the regulated value cannot be cleared.
Further, the mounting of the EMI countermeasure components on a printed circuit board may result in an increase in the occupied area thereof and the cost. In a situation where a lot of the semiconductor integrated circuits are synchronized with a clock signal, an SSCG technique for modulating a clock frequency to reduce a peak spectrum thereof is drawing attention.
FIG. 9 is a diagram showing a configuration described in Patent Document 1.
Reference numeral Y1 31 denotes a piezoelectric crystal used in an oscillation circuit 32, and generates a stable clock pulse train or an unmodulated clock signal. A first programmable counter 35 divides (frequency divides) the unmodulated clock signal by an integer number (M). A clock signal output from a voltage controlled oscillator 39 (VCO) for adjusting an oscillation frequency based on a voltage from a filter 38 is supplied to a buffer 40. From the buffer 40, an output clock is output. The frequency of the clock signal is proportional to an input voltage from a phase comparator 37 and the filter 38. The clock signal output from the VCO 39 is supplied to a second programmable counter 42, where the clock signal from the VCO 39 is frequency divided by an integer number (N), for supply to the phase comparator 37.
The phase comparator 37 and the filter 38 generate an analog signal that is proportional to the phase in error between the first programmable counter 35 and the second programmable counter 42, respectively. The clock signal from the buffer is thus equal to the oscillator frequency times (N/M). Spread spectrum modulation is performed using spread spectrum modulation means 41 that changes the M and the N as a function of time. A third programmable counter 45 divides the output of an oscillating circuit 32 by an integer number (I) that sets the rate that the M and the N change or modulation frequency.
First and second look-up tables 46 and 47 are, respectively, the stabilized values of the M and the N that modulate the frequency of the output clock signal.
An up/down counter 49 is used to index successive entries in the look-up tables. A serial link 51 may be used to program different values in the programmable counters or look-up tables to modify modulation characteristics.
FIG. 10 is a diagram showing other configuration described in Patent Document 1. The spread spectrum modulation is performed by a second VCO 52 and an analog modulated signal, which is the output of a digital to analog converter 83 (DAC).
In case of no modulation, the second VCO 52 creates a clock signal identical to the first VCO 39. The second VCO 51 responds to the analog modulation to thereby create the spread spectrum clock output signal.
The modulation is performed through the use of a ROM 82 that stores modulation amplitude values that are fed into the digital to analog converter 83. The count output of an up/down counter 84 is used as an address in the ROM 82. A third programmable counter 85 sets the modulation frequency.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-7-235862 (FIGS. 6 and 9)